idesignspec for Windows 10


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IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec's PATENT PENDING technology improves engineer's productivity and design quality.

Key Benefits

* Automatically Verify all addressable registers in the design
* Create synthesizable code for registers
* Get a jump start for Device Driver, Firmware and application software development
* Automatically create documentation for customers and Tech-Pubs
* Improves productivity of engineers and quality of results.
* Supports Architecture, Design, Verification, Diagnostics, Firmware, Application Software and Documentation groups.

Key Features

* Easy to use Plugin for all popular Editors. No need for any new tool, and no new language to learn.
* Transformations possible out of the box:

o Verilog, VHDL synthesizable design code for industry standard bus protocols (AMBA-AHB, AVALON, and Proprietary)
o Test bench files for OVM, VMM, UVM, eRM (vr_ad)
o C header files, and C++ Class files for Firmware and Device Drivers
o HTML and PDF documentation
o SystemC, SystemVerilog based Verification code (based on UVM, OVM and VMM methodology)
o IP-XACT output conforming to Spirit Consortium
o SystemRDL standard output

* Imports : IP-XACT, SystemRDL, XML, CSV
* Register data stored in native editor format, not locked to Agnisys. Provides complete register data portability.
* Extensible: User defined transformations are possible using Tcl or XSLT.